Oxide thin film transistor, display panel and preparation method thereof

ABSTRACT

The present application discloses an oxide thin film transistor, a display panel, and a preparation method thereof. Each thickness of the first gate insulating layer of the present application corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region; and thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region. The the first gate insulating layer effectively shields the first channel region laterally.

TECHNICAL FIELD

The present application relates to a technical field of display, and inparticular, to an oxide thin film transistor, a display panel, and apreparation method thereof.

BACKGROUND

Thin film transistor (TFT) is an important part of a flat panel displaydevice, which can be provided on a glass substrate or a plasticsubstrate and is usually used as a switching device and a driving devicein a driving circuit of a display panel. In order to improve productimage quality and reduce product power consumption, designers integratea low-temperature polysilicon (LTPS) thin film transistor and a metaloxide thin film transistor on a same driving circuit layer, which cancombine the advantages of high mobility and fast charging speed forpixel capacitors of a low-temperature polysilicon thin film transistor,and low leakage current of a metal oxide thin film transistor.

A metal oxide semiconductor layer without special treatment has a largesquare resistance, which affects resistances of source and drainregions, thus affecting the mobility. In order to reduce blockresistance of a metal oxide, source and drain regions are usuallytreated. For example, boron ion doping is used to reduce blockresistance of source and drain regions, so as to make them conductive.Boron ions will diffuse from source and drain regions to a channelregion, resulting in shortening of an actual channel region, which willseriously affect the threshold voltage of a device, and thus affecting apreparation process. As shown in FIGS. 1 and 2 , a metal oxide thin filmtransistor 10 comprises a second gate 11, a first sub-buffer layer 12-1,a second sub-buffer layer 12-2, a metal oxide semiconductor layer, agate insulating layer 14, a first gate 15, a first inter-sub-layerinsulating layer 16-1, a second inter-sub-layer insulating layer 16-2, asource 17, and a drain 18. A metal oxide semiconductor layer comprises asource doped region 13-1, a drain doped region 13-3, and a channelregion 13-2. In a top view of a channel region 13-2 in FIG. 2 , thefirst gate 15 is located at an intermediate position of the second gate11. As boron ions will diffuse from the source doped region 13-1 and thedrain doped region 13-3 to the channel region 13-2, a first diffusionregion 13-4 is generated between the source doped region 13-1 and thechannel region 13-2, and a second diffusion region 13-5 is generatedbetween the drain doped region 13-3 and the channel region 13-2.Assuming that length of a channel 13-2 is originally designed as L andits diffusion length is AL, then length of the remaining actual channel13-2 becomes (L-2ΔL).

Therefore, it is necessary to design a new oxide thin film transistor, adisplay panel and a preparation method thereof, so as to solve the abovetechnical problems that a gate insulating layer is patterned by using agate self-alignment method, and then source and drain regions are dopedwith conductive ions to reduce its block resistance and make themconductive, and the doped conductive ions will diffuse alongsource/drain regions to a channel region, resulting in shortening of anactual channel region, which will seriously affect the threshold voltageof a device and stability of an electrical signal of a driving circuitlayer.

Technical Problem

An embodiment of the present application provides an oxide thin filmtransistor, a display panel and a preparation method thereof, which cansolve a problem that source and drain regions of a metal oxide thin filmtransistor in a existing driving circuit layer is doped with conductiveions, which will diffuse to along source and drain regions to a channelregion, resulting in shortening of an actual channel region, which willseriously affect the threshold voltage of a device.

Technical Solution

To solve the above problems, the present application provides technicalsolutions as follows: An embodiment of the present application providean oxide thin film transistor, comprising a substrate, a first activelayer on the substrate, a first gate insulating layer disposed on oneside of the first active layer away from the substrate, a first gatedisposed on one side of the first gate insulating layer away from thesubstrate, a first interlayer insulating layer disposed on one side ofthe first gate away from the substrate, and a source/drain layerdisposed on one side of the first interlayer insulating layer away fromthe substrate, wherein the source/drain layer comprises a first sourceand a first drain;

-   -   the first active layer comprises a first source doped region, a        first channel region, a first drain doped region, a first        diffusion region between the first source doped region and the        first channel region, and a second diffusion region between the        first drain doped region and the first channel region; wherein        the first source is electrically connected to the first source        doped region, and the first drain is electrically connected to        the first drain doped region;    -   each thickness of the first gate insulating layer corresponding        to the first source doped region, the first drain doped region,        the first diffusion region, and the second diffusion region is        less than a thickness corresponding to the first channel region;        and    -   thicknesses of the first gate insulating layer corresponding to        the first diffusion region and the second diffusion region are        both different from a thickness corresponding to the first        source doped region and the first drain doped region.

According to a preferred embodiment of the present application, both ofthicknesses of the first gate insulating layer corresponding to thefirst diffusion region and the second diffusion region are greater thana thickness corresponding to the first source doped region and the firstdrain doped region.

According to a preferred embodiment of the present application, thefirst active layer is doped with a conductive particle;

-   -   both of doping concentrations of the conductive particle in the        first source doped region and the first drain doped region are        greater than doping concentrations of the conductive particle in        the first diffusion region and the second diffusion region; and    -   both of doping concentrations of the conductive particle in the        first diffusion region and the second diffusion region are        greater than doping concentration of the conductive particle in        the first channel region.

According to a preferred embodiment of the present application, thefirst gate insulating layer is provided with a first step correspondingto the first source doped region and the first drain doped region, thefirst gate insulating layer is provided with a second step correspondingto the first diffusion region and the second diffusion region, and oneside of the second step close to the first channel region is flush withone side of the first gate.

According to a preferred embodiment of the present application, both ofthe first source doped region and the first drain doped region are dopedwith boron ions, wherein a concentration of the boron ions ranges from1×10¹² ions/cm² to 1×10¹⁴ ions/cm².

According to a preferred embodiment of the present application, a heightof the second step is greater than a height of the first step.

According to a preferred embodiment of the present application, theconductive particle comprises one of boron ions, nitrogen ions orphosphorus ions.

According to the oxide thin film transistor in the above embodiments, anembodiment of the present application further provides a display panelcomprising:

-   -   a substrate;    -   a driving circuit layer disposed on one side of a substrate, and        the driving circuit layer comprises a first active layer, a        first gate insulating layer disposed on one side of the first        active layer away from the substrate, a first gate disposed on        one side of the first gate insulating layer away from the        substrate, a first interlayer insulating layer disposed on one        side of the first gate away from the substrate, and a        source/drain layer disposed on one side of the first interlayer        insulating layer away from the substrate, wherein the        source/drain layer comprises a first source and a first drain;    -   wherein the first active layer comprises a first source doped        region, a first channel region, a first drain doped region, a        first diffusion region between the first source doped region and        the first channel region, and a second diffusion region between        the first drain doped region and the first channel region;        wherein the first source is electrically connected to the first        source doped region, and the first drain is electrically        connected to the first drain doped region;    -   each thickness of the first gate insulating layer corresponding        to the first source doped region, the first drain doped region,        the first diffusion region, and the second diffusion region is        less than a thickness corresponding to the first channel region;        and    -   thicknesses of the first gate insulating layer corresponding to        the first diffusion region and the second diffusion region are        both different from a thickness corresponding to the first        source doped region and the first drain doped region.

According to a preferred embodiment of the present application, both ofthicknesses of the first gate insulating layer corresponding to thefirst diffusion region and the second diffusion region are greater thanthicknesses of the first source doped region and the first drain dopedregion corresponding to the first gate insulating layer.

According to a preferred embodiment of the present application, thefirst active layer is doped with a conductive particle;

-   -   both of doping concentrations of the conductive particle in the        first source doped region and the first drain doped region are        greater than that doping concentrations of the conductive        particle in the first diffusion region and the second diffusion        region; and    -   both of doping concentrations of the conductive particle in the        first diffusion region and the second diffusion region are        greater than doping concentration of the conductive particle in        the first channel region.

According to a preferred embodiment of the present application, thefirst gate insulating layer is provided with a first step correspondingto the first source doped region and the first drain doped region, thefirst gate insulating layer is provided with a second step correspondingto the first diffusion region and the second diffusion region, and oneside of the second step close to the first channel region is flush withone side of the first gate.

According to a preferred embodiment of the present application, thedrive circuit layer comprises a second gate between the substrate andthe first active layer.

According to a preferred embodiment of the present application, thedrive circuit layer further comprises at least a second active layer, athird gate, a fourth gate, a second source and a second drain disposedabove the substrate, the second gate and the fourth gate are disposed ina same layer, and the first source, the first drain, the second sourceand the second drain are disposed in a same layer.

According to a preferred embodiment of the present application, thefirst active layer is a metal oxide semiconductor layer, and the secondactive layer is a low-temperature polysilicon semiconductor layer.

According to a preferred embodiment of the present application, thedriving circuit layer further comprises a light shielding electrodelayer, the light shielding electrode layer covers the first activelayer, and the light shielding electrode layer is electrically connectedto the second source.

According to a preferred embodiment of the present application, theconductive particle comprises one of boron ions, nitrogen ions, orphosphorus ions.

According to a preferred embodiment of the present application, thelight shielding electrode layer comprises one of molybdenum, copper,chromium, tungsten, tantalum, or titanium.

According to the display panel in the above embodiments, the presentapplication further provides a method for preparing a display panel,wherein the method comprises:

-   -   step S1: providing a substrate, and forming at least a first        active layer, a first gate insulating layer, a first gate layer,        and a photoresist layer on the substrate; wherein the first        active layer comprises a first source doped region, a first        channel region, a first drain doped region, a first diffusion        region between the first source doped region and the first        channel region, and a second diffusion region between the first        drain doped region and the first channel region;    -   step S2: patterning the photoresist layer to form a first        photoresist pattern that does not block the first source doped        region and the first drain doped region of the first active        layer;    -   step S3: etching the first gate layer and the first gate        insulating layer by using the first photoresist pattern as a        barrier layer, so that both thicknesses of the first gate        insulating layer corresponding to the first source doped region        and the first drain doped region are smaller than a thickness        corresponding to the first diffusion region, the second        diffusion region, and the first channel region; and        simultaneously doping a conductive particle from the first gate        insulating layer to the first source doped region and the first        drain doped region;    -   step S4: patterning the first photoresist pattern to form a        second photoresist pattern, etching a first quasi-gate and the        first gate insulating layer by using the first photoresist        pattern as a barrier layer again, so that each thickness of the        first gate insulating layer corresponding to the first diffusion        region and the second diffusion region is less than a        thicknesses corresponding to the first channel region; and        stripping the second photoresist pattern; and    -   step S5: forming an interlayer insulating layer on the first        gate insulating layer, and forming a first source and a first        drain on the interlayer insulating layer, wherein the first        source and the first drain are electrically connected to the        first source doped region and the first drain doped region        through a source contact hole and a drain contact hole,        respectively.

According to a preferred embodiment of the present application, theconductive particle in the step S3 comprises one of boron ions, nitrogenions, or phosphorus ions.

According to a preferred embodiment of the present application, both ofdoping concentrations of the conductive particle in the first sourcedoped region and the first drain doped region are greater than thatdoping concentrations of the conductive particle in the first diffusionregion and the second diffusion region; and both of dopingconcentrations of the conductive particle in the first diffusion regionand the second diffusion region are greater than doping concentration ofthe conductive particle in the first channel region.

Technical Effects

An embodiment of the present application provide an oxide thin filmtransistor, a display panel, and a preparation method thereof. The firstactive layer comprises a first source doped region, a first channelregion, a first drain doped region, a first diffusion region between thefirst source doped region and the first channel region, and a seconddiffusion region between the first drain doped region and the firstchannel region. Each thickness of the first gate insulating layercorresponding to the first source doped region, the first drain dopedregion, the first diffusion region, and the second diffusion region isless than a thickness corresponding to the first channel region; andthicknesses of the first gate insulating layer corresponding to thefirst diffusion region and the second diffusion region are bothdifferent from a thickness corresponding to the first source dopedregion and the first drain doped region, so that the first gateinsulating layer effectively shields the first channel region laterally,and a distance for lateral diffusion of conductive ions along thechannel region is reserved, which can effectively prevent the channelregion from being shortened, ensure that the channel region has aneffective length, and prevent threshold voltage from drifting.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly describe the technical solutions in theembodiments or the prior art, hereinafter, the appended drawings usedfor describing the embodiments or the prior art will be brieflyintroduced. Apparently, the appended drawings described below are onlydirected to some embodiments of the present application, and for aperson skilled in the art, without expenditure of creative labor, otherdrawings can be derived on the basis of these appended drawings.

FIG. 1 is a schematic structural diagram of an oxide thin filmtransistor according to the prior art.

FIG. 2 is a schematic top view of a channel region of an oxide thin filmtransistor according to the prior art.

FIG. 3 is a schematic structural diagram of an oxide thin filmtransistor according to an embodiment of the present application.

FIG. 4 is a schematic top view of a channel region of an oxide thin filmtransistor according to an embodiment of the present application.

FIG. 5 is a schematic structural diagram of a display panel according toan embodiment of the present application.

FIGS. 6-13 are schematic diagrams of a local structure in a preparationprocess flow of a display panel according to an embodiment of thepresent application.

DETAILED DESCRIPTION

Hereinafter, technical solution in embodiments of the presentapplication will be clearly and completely described with reference tothe accompanying drawings in embodiments of the present application.Apparently, the described embodiments are part of, but not all of, theembodiments of the present application. All the other embodiments,obtained by a person with ordinary skill in the art on the basis of theembodiments in the present application without expenditure of creativelabor, belong to the protection scope of the present application.

Indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. canbe used as an active layer material of a thin film transistor. Comparedwith an amorphous silicon thin film transistor, carrier concentration ofan oxide thin film transistor is about ten times that of an amorphoussilicon thin film transistor, and carrier mobility of an oxide thin filmtransistor is 20-30 times that of an amorphous silicon thin filmtransistor. Therefore, an oxide thin film transistor can greatly improvecharge-discharge rate of a thin film transistor to a pixel electrode,improve response rate of a pixel, and further achieve a faster refreshrate. An oxide thin film transistor can meet the requirements ofapplications that require a fast response and a relative large current,such as high-frequency, high-resolution, large-size displays and organiclight-emitting displays. However, after doping with conductive particlesin a doped region of metal oxide thin film transistors prepared by anexisting technology, conductive particles will diffuse along source anddrain doped regions to a channel region, resulting in shortening of anactual channel region length, which will seriously affect the thresholdvoltage of a device. This embodiment can solve this problem.

As shown in FIG. 3 , an embodiment of the present application provides aschematic structural diagram of an oxide thin film transistor 100comprising a substrate 101, a second gate 102 on the substrate 101, abuffer layer 103 on the second gate 102, a first active layer 104 on thebuffer layer 103, a first gate insulating layer 105 on the buffer layer103 and covering the first active layer 104, a first gate 108 on thefirst gate insulating layer 105, an interlayer insulating layer 109 onthe first gate insulating layer 105 and covering the first gate 108, afirst source 111 and a first drain 112 on the interlayer insulatinglayer 109. The first active layer 104 comprises a first source dopedregion 1041, a first channel region 1042, a first drain doped region1043, a first diffusion region 1044 between the first source dopedregion 1041 and the first channel region 1042, and a second diffusionregion 1045 between the first drain doped region 1043 and the firstchannel region 1042. The first source 111 is electrically connected tothe first source doped region 1041, and the first drain 112 iselectrically connected to the first drain doped region 1043.

A material of the first active layer 104 is preferably selected from thegroup consisting of indium gallium zinc oxide, indium zinc oxide,gallium zinc oxide, and any combination thereof. The substrate 101comprises a first transparent polyimide film, a first water-blockinglayer, a second transparent polyimide film, and a second water-blockinglayer which are stacked. The buffer layer 103 comprises a first siliconnitride layer 1031 and a second silicon oxide layer 1032. The interlayerinsulating layer 109 comprises a silicon oxide layer 1091 and a siliconnitride layer 1092.

Each thickness of the first gate insulating layer 105 corresponding tothe first source doped region 1041, the first drain doped region 1043,the first diffusion region 1044, and the second diffusion region1045 isless than a thickness corresponding to the first channel region 1042.Thicknesses of the first gate insulating layer 105 corresponding to thefirst diffusion region 1044 and the second diffusion region 1045 areboth different from a thickness corresponding to the first source dopedregion 1041 and the first drain doped region 1043. Specifically, both ofthicknesses of the first gate insulating layer 105 corresponding to thefirst diffusion region 1044 and the second diffusion region 1045 aregreater than a thickness corresponding to the first source doped region1041 and the first drain doped region 1043. In this embodiment, bychanging thickness of the first gate insulating layer 105 on the firstactive layer 104, the first channel region 1042 can be effectivelyshielded laterally, and a distance for lateral diffusion of conductiveions along the channel region is reserved, which can effectively preventthe channel region from being shortened, ensure that the channel regionhas an effective length, and prevent threshold voltagefrom drifting.

The first active layer 104 is doped with a conductive particle. Both ofdoping concentrations of the conductive particle in the first sourcedoped region 1041 and the first drain doped region 1043 are greater thandoping concentrations of the conductive particle in the first diffusionregion 1044 and the second diffusion region 1045; and both of dopingconcentrations of the conductive particle in the first diffusion region1044 and the second diffusion region 1045 are greater than dopingconcentration of the conductive particle in the first channel region1042. The conductive particle comprises one of boron ions, nitrogen ionsor phosphorus ions.

The first gate insulating layer 105 is provided with a first step 106corresponding to the first source doped region 1041 and the first draindoped region 1043. The first gate insulating layer 105 is provided witha second step 107 corresponding to the first diffusion region 1044 andthe second diffusion region 1045. One side of the second step 107 closeto the first channel region 1042 is flush with one side of the firstgate 108. A height H2 of the second step 107 is greater than a height H1of the first step 106. Specifically, the first gate insulating layer 105is provided with a left first step 1061 corresponding to the firstsource doped region 1041, the first gate insulating layer 105 isprovided with a right first step 1062 corresponding to the first draindoped region 1043, and the left first step 1061 and the right first step1062 form the first step 106. The first gate insulating layer 105 isprovided with a left second step 1071 corresponding to the firstdiffusion region 1044, the first gate insulating layer 105 is providedwith a right second step 1072 corresponding to the second diffusionregion 1045, and both of opposite sides of the right second step 1072and the left second step 1071 are flush with one side of the first gate108. A length of the left second step 1071 is greater than or equal to alength of the first diffusion region 1044, a length of the right secondstep 1072 is greater than or equal to a length of the second diffusionregion 1045, and the left second step 1071 and the right second step1072 form a second step 107.

As shown in FIG. 4 , an embodiment of the present application provides aschematic top view of a channel region of an oxide thin film transistor100. In the schematic top view of the channel region, the first gate 108is located directly above the first active layer 104, and the first gate108 is located in the middle of the second gate 102. The first gate 108overlaps with the first channel region 1042. The first source 111 iselectrically connected to the first source doped region 1041 through asource contact hole, and the first drain electrode 112 is electricallyconnected to the first drain doped region 1043 through a drain contacthole.

As shown in FIG. 5 , according to the oxide thin film transistor 100 inthe above-described embodiments, the present application furtherprovides a display panel 300. The applicant fabricated the oxide thinfilm transistor 100 and the low-temperature polysilicon thin filmtransistor 200 at the same time on a same driving circuit layer of thedisplay panel 300. In particular, structure of the oxide thin filmtransistor 100 is the same as that in FIG. 3 . The oxide thin filmtransistor 100 and the low-temperature polysilicon thin film transistor200 have a plurality of film layers arranged in a same layer, and thereference numerals herein overlap. The display panel 300 comprises asubstrate 101 and a driving circuit layer on one side of the substrate101.

Combining FIG. 5 and FIG. 3 , the driving circuit layer comprises afirst active layer 104, a first gate insulating layer 105 disposed onone side of the first active layer 104 away from the substrate 101, afirst gate 108 disposed on one side of the first gate insulating layer105 away from the substrate 101, a first interlayer insulating layerdisposed on one side of the first gate 108 away from the substrate 301,and a source/drain layer disposed on one side of the first interlayerinsulating layer away from the substrate, wherein the source/drain layercomprises a first source 111 and a first drain 112. The first activelayer 104 comprises a first source doped region 1041, a first channelregionl 042, a first drain doped region 1043, a first diffusion region1044 between the first source doped region 1041 and the first channelregion 1042, and a second diffusion region 1045 between the first draindoped region 1043 and the first channel region 1042, wherein the firstsource 111 is electrically connected to the first source doped region1041, and the first drain 112 is electrically connected to the firstdrain doped region 1043. Each thickness of the first gate insulatinglayer 105 corresponding to the first source doped region 1041, the firstdrain doped region 1043, the first diffusion region 1044, and the seconddiffusion region 1045 is less than a thickness corresponding to thefirst channel region 1042. Thicknesses of the first gate insulatinglayer 105 corresponding to the first diffusion region 1044 and thesecond diffusion region 1045 are both different from a thicknesscorresponding to the first source doped region 1041 and the first draindoped region 1043. Both of thicknesses of the first gate insulatinglayer 105 corresponding to the first diffusion region 1044 and thesecond diffusion region 1045 is greater than thicknesses of the firstsource doped region 1041 and the first drain doped region 1043corresponding to the first gate insulating layer 105. The first gateinsulating layer 105 between the first gate 108 and the first activelayer 104 comprises a first step 106 and a second step 107 above thefirst step 106. Specific structures of the first step 106 and the secondstep 107 are not described herein again. In this embodiment, by changingthickness of the first gate insulating layer 105 on the first activelayer 104, the first channel region 1042 can be effectively shieldedlaterally, and a distance for lateral diffusion of conductive ions alongthe channel region is reserved, which can effectively prevent thechannel region from being shortened, ensure that the channel region hasan effective length, and prevent threshold voltagefrom drifting.

The first active layer 104 is doped with a conductive particle. Both ofdoping concentrations of the conductive particle in the first sourcedoped region 1041 and the first drain doped region 1043 are greater thandoping concentrations of the conductive particle in the first diffusionregion 1044 and the second diffusion region 1045. Both of dopingconcentrations of the conductive particle in the first diffusion region1044 and the second diffusion region 1045 are greater than dopingconcentration of the conductive particle in the first channel region1042. The conductive particle comprises one of boron ions, nitrogen ionsor phosphorus ions.

The driving circuit layer comprises a second gate 102 between thesubstrate 101 and the first active layer 104. The driving circuit layerfurther comprises at least a second active layer 201, a third gate 203,a fourth gate 205, a second source 206, and a second drain 207 disposedabove the substrate 101, the second gate 102 and the fourth gate 205 aredisposed in a same layer, and the first source 111, the first drain 112,the second source 206, and the second drain 207 are disposed in a samelayer. The first active layer 104 is a metal oxide semiconductor layer,and the second active layer 201 is a low-temperature polysiliconsemiconductor layer. The driving circuit layer further comprises a lightshielding electrode layer 302, the light shielding electrode layer 302covers the first active layer 102, and the light shielding electrodelayer 102 is electrically connected to the second source 206. A materialof the light shielding electrode layer 302 comprises one of molybdenum,copper, chromium, tungsten, tantalum, or titanium.

Specifically, substrate 101 in this embodiment comprises a firstpolyimide (PI) layer 1011, a first water-blocking layer 1012 on thefirst PI layer 1011, a second polyimide (PI) layer 1013 on the firstwater-blocking layer 1012, a second water-blocking layer 1014 on thesecond polyimide (PI) layer 1013, a silicon nitride layer 1015 on thesecond water-blocking layer 1014, and a silicon oxide layer 1016 on thesilicon nitride layer 1015. A third gate insulating layer 202 coveringthe second active layer 201 is disposed on the silicon oxide layer 1016,and a fourth gate insulating layer 204 covering the third gate 203 isdisposed on the third gate insulating layer 202. The third gateinsulating layer 202 is a silicon oxide layer, and the fourth gateinsulating layer 204 is a silicon nitride layer. The interlayerinsulating layer 205 comprises a silicon nitride layer 2051, a siliconoxide layer 2052, a first gate insulating layer 105, a silicon oxidelayer 2053, and a silicon nitride layer 2054. The interlayer insulatinglayer 205 is provided with a first planarization layer 301 of the firstsource electrode 111, a first drain 112, a second source 206, and asecond drain 207, and the first planarization layer 301 is provided witha light shielding electrode layer 302 and an auxiliary electrode 303. Asecond planarization layer 304 is further provided above the lightshielding electrode layer 302 and the auxiliary electrode 303. An anode305 and a pixel definition layer 306 are provided on the secondplanarization layer 304. A pixel opening 308 is provided on the pixeldefinition layer 306 corresponding to the position of the anode 305, alight emitting device (not shown) is provided on the pixel opening 308,and spacers 307 are provided on both sides of the pixel definition layer306 corresponding to the pixel opening 308. In this embodiment, thedisplay panel 300 further comprises an encapsulation layer covering thelight emitting device and a polarizing layer on the surface of the anencapsulation layer.

According to the display panel 300 in the above-described embodiment,the present application further provides a method for preparing adisplay panel, the display panel comprises a substrate and a drivecircuit layer on one side of the substrate, wherein the methodcomprises:

-   -   step S1: providing a substrate, and forming at least a first        active layer, a first gate insulating layer, a first gate layer,        and a photoresist layer on the substrate; wherein the first        active layer comprises a first source doped region, a first        channel region, a first drain doped region, a first diffusion        region between the first source doped region and the first        channel region, and a second diffusion region between the first        drain doped region and the first channel region;    -   step S2: patterning the photoresist layer to form a first        photoresist pattern that does not block the first source doped        region and the first drain doped region of the first active        layer;    -   step S3: etching the first gate layer and the first gate        insulating layer by using the first photoresist pattern as a        barrier layer, so that both thicknesses of the first gate        insulating layer corresponding to the first source doped region        and the first drain doped region are smaller than a thickness        corresponding to the first diffusion region, the second        diffusion region, and the first channel region; and        simultaneously doping a conductive particle from the first gate        insulating layer to the first source doped region and the first        drain doped region;    -   step S4: patterning the first photoresist pattern to form a        second photoresist pattern, etching a first quasi-gate and the        first gate insulating layer by using the first photoresist        pattern as a barrier layer again, so that each thickness of the        first gate insulating layer corresponding to the first diffusion        region and the second diffusion region is less than a        thicknesses corresponding to the first channel region; and        stripping the second photoresist pattern; and    -   step S5: forming an interlayer insulating layer on the first        gate insulating layer, and forming a first source and a first        drain on the interlayer insulating layer, wherein the first        source and the first drain are electrically connected to the        first source doped region and the first drain doped region        through a source contact hole and a drain contact hole,        respectively.

FIGS. 6-13 are schematic structural diagrams of a film layer preparationflow of an oxide thin film transistor in a display panel according to anembodiment of the present application. In particular, structure of theoxide thin film transistor 100 is the same as that in FIG. 5 . The oxidethin film transistor 100 and the low-temperature polysilicon thin filmtransistor 200 have a plurality of film layers arranged in a same layer,and the reference numerals herein overlap. In this embodiment, thereference numerals are subjected to those in FIGS. 6-13 .

As shown in FIG. 6 , a substrate 101 is provided, a second gate 102 anda silicon nitride layer 1031 covering the second gate 102 are preparedon the substrate 101, a silicon oxide layer 1032 is prepared on thesilicon nitride layer 1031, the silicon nitride layer 1031 and thesilicon oxide layer 1032 form a buffer layer 103, a first active layer104 and a first gate insulating layer 105 covering the first activelayer 104 are prepared on the buffer layer 103, a second gate layer 1080is prepared on the first gate insulating layer 105, and a photoresistlayer 113 is prepared on the second gate layer 1080.

As shown in FIGS. 7 and 8 , the first active layer 104 comprises a firstsource doped region 1041, a first channel region 1042, a first draindoped region 1043, a first diffusion region 1044 between the firstsource doped region 1041 and the first channel region 1042, and a seconddiffusion region 1045 between the first drain doped region 1043 and thefirst channel region 1042. The photoresist layer 113 is patterned toform a first photoresist pattern 1131 that does not block the firstsource doped region 1041 and the first drain doped region 1042 of thefirst active layer 104. The second gate layer 1080 and the first gateinsulating layer 105 are etched by using the first photoresist pattern1131 as a barrier layer to form a second quasi-gate 1081, a left firststep 1061 above the first source doped region 1041, and a right firststep 1062 above the first drain doped region 1043, and the left firststep 1061 and the right first step 1062 form a step 106. Then the firstphotoresist pattern layer 1131, the second quasi-gate 1081 and the firststep 106 are used as shielding layers, and a conductive particle isdoped from the first gate insulating layer to the first source dopedregion 1041 and the first drain doped region 1043 simultaneously,wherein a concentration of the boron ions preferably ranges from 1×10¹²ions/cm² to 1×10¹⁴ ions/cm². The conductive particle comprises one ofboron ions, nitrogen ions or phosphorus ions. Both of dopingconcentrations of the conductive particle in the first source dopedregion 1041 and the first drain doped region 1043 are greater than thatdoping concentrations of the conductive particle in the first diffusionregion 1044 and the second diffusion region 1045, and both of dopingconcentrations of the conductive particle in the first diffusion region1044 and the second diffusion region 1045 are greater than dopingconcentration of the conductive particle in the first channel region1042.

As shown in FIGS. 9, 10 and 11 , the first photoresist pattern 1131 ispatterned to form a second photoresist pattern 1132, and the secondquasi-gate 1081 and the first gate insulating layer 105 are etched againby using the second photoresist pattern 1132 as a barrier layer to forma required first gate 108 and a second step 107 over the first diffusionregion 1044 and the second diffusion region 1045, wherein the secondstep 107 comprises a left second step 1071 and a right second step 1072,and the second photoresist pattern 1132 is stripped.

As shown in FIGS. 12 and 13 , an interlayer insulating layer 109 isformed on the first gate insulating layer 105, the interlayer insulatinglayer 109 comprises a silicon oxide layer 1091 and a silicon nitridelayer 1092, a source contact hole 1110 and a drain contact hole 1120 areetched on the interlayer insulating layer 109, a first source 111 and afirst drain 112 are provided on the interlayer insulating layer 109, thefirst source 111 and the first drain 112 are electrically connected tothe first source doped region 1141 and the first drain doped region 1143through the source contact hole 1110 and the drain contact hole 1120,respectively, thereby completing the film layer preparation of thecorresponding oxide thin film transistor 100 in the driving circuitlayer.

In summary, although the present application has been disclosed as abovepreferred embodiments, the above preferred embodiments are not intendedto limit the present application, and a skilled person in the art maymake various modifications without departing from the spirit and scopeof the present application. Therefore, the protection scope of thepresent application is subject to the scope defined by the claims.

What is claimed is:
 1. An oxide thin film transistor, comprising asubstrate, a first active layer on the substrate, a first gateinsulating layer disposed on one side of the first active layer awayfrom the substrate, a first gate disposed on one side of the first gateinsulating layer away from the substrate, a first interlayer insulatinglayer disposed on one side of the first gate away from the substrate,and a source/drain layer disposed on one side of the first interlayerinsulating layer away from the substrate, wherein the source/drain layercomprises a first source and a first drain; the first active layercomprises a first source doped region, a first channel region, a firstdrain doped region, a first diffusion region between the first sourcedoped region and the first channel region, and a second diffusion regionbetween the first drain doped region and the first channel region;wherein the first source is electrically connected to the first sourcedoped region, and the first drain is electrically connected to the firstdrain doped region; each thickness of the first gate insulating layercorresponding to the first source doped region, the first drain dopedregion, the first diffusion region, and the second diffusion region isless than a thickness corresponding to the first channel region; andthicknesses of the first gate insulating layer corresponding to thefirst diffusion region and the second diffusion region are bothdifferent from a thickness corresponding to the first source dopedregion and the first drain doped region.
 2. The oxide thin filmtransistor according to claim 1, wherein both of thicknesses of thefirst gate insulating layer corresponding to the first diffusion regionand the second diffusion region are greater than a thicknesscorresponding to the first source doped region and the first drain dopedregion.
 3. The oxide thin film transistor according to claim 1, whereinthe first active layer is doped with a conductive particle; both ofdoping concentrations of the conductive particle in the first sourcedoped region and the first drain doped region are greater than dopingconcentrations of the conductive particle in the first diffusion regionand the second diffusion region; and both of doping concentrations ofthe conductive particle in the first diffusion region and the seconddiffusion region are greater than doping concentration of the conductiveparticle in the first channel region.
 4. The oxide thin film transistoraccording to claim 1, wherein the first gate insulating layer isprovided with a first step corresponding to the first source dopedregion and the first drain doped region, the first gate insulating layeris provided with a second step corresponding to the first diffusionregion and the second diffusion region, and one side of the second stepclose to the first channel region is flush with one side of the firstgate.
 5. The oxide thin film transistor according to claim 3, whereinboth of the first source doped region and the first drain doped regionare doped with boron ions, wherein a concentration of the boron ionsranges from 1×10¹² ions/cm² to 1×10¹⁴ ions/cm².
 6. The oxide thin filmtransistor according to claim 4, wherein a height of the second step isgreater than a height of the first step.
 7. The oxide thin filmtransistor according to claim 3, wherein the conductive particlecomprises one of boron ions, nitrogen ions or phosphorus ions.
 8. Adisplay panel, comprising: a substrate; a driving circuit layer disposedon one side of a substrate, and the driving circuit layer comprises afirst active layer, a first gate insulating layer disposed on one sideof the first active layer away from the substrate, a first gate disposedon one side of the first gate insulating layer away from the substrate,a first interlayer insulating layer disposed on one side of the firstgate away from the substrate, and a source/drain layer disposed on oneside of the first interlayer insulating layer away from the substrate,wherein the source/drain layer comprises a first source and a firstdrain; wherein the first active layer comprises a first source dopedregion, a first channel region, a first drain doped region, a firstdiffusion region between the first source doped region and the firstchannel region, and a second diffusion region between the first draindoped region and the first channel region; wherein the first source iselectrically connected to the first source doped region, and the firstdrain is electrically connected to the first drain doped region; eachthickness of the first gate insulating layer corresponding to the firstsource doped region, the first drain doped region, the first diffusionregion, and the second diffusion region is less than a thicknesscorresponding to the first channel region; and thicknesses of the firstgate insulating layer corresponding to the first diffusion region andthe second diffusion region are both different from a thicknesscorresponding to the first source doped region and the first drain dopedregion.
 9. The display panel according to claim 8, wherein both ofthicknesses of the first gate insulating layer corresponding to thefirst diffusion region and the second diffusion region are greater thanthicknesses of the first source doped region and the first drain dopedregion corresponding to the first gate insulating layer.
 10. The displaypanel according to claim 8, wherein the first active layer is doped witha conductive particle; both of doping concentrations of the conductiveparticle in the first source doped region and the first drain dopedregion are greater than that doping concentrations of the conductiveparticle in the first diffusion region and the second diffusion region;and both of doping concentrations of the conductive particle in thefirst diffusion region and the second diffusion region are greater thandoping concentration of the conductive particle in the first channelregion.
 11. The display panel according to claim 8, wherein the firstgate insulating layer is provided with a first step corresponding to thefirst source doped region and the first drain doped region, the firstgate insulating layer is provided with a second step corresponding tothe first diffusion region and the second diffusion region, and one sideof the second step close to the first channel region is flush with oneside of the first gate.
 12. The display panel according to claim 8,wherein the drive circuit layer comprises a second gate between thesubstrate and the first active layer.
 13. The display panel according toclaim 12, wherein the drive circuit layer further comprises at least asecond active layer, a third gate, a fourth gate, a second source and asecond drain disposed above the substrate, the second gate and thefourth gate are disposed in a same layer, and the first source, thefirst drain, the second source and the second drain are disposed in asame layer.
 14. The display panel according to claim 13, wherein thefirst active layer is a metal oxide semiconductor layer, and the secondactive layer is a low-temperature polysilicon semiconductor layer. 15.The display panel according to claim 13, wherein the driving circuitlayer further comprises a light shielding electrode layer, the lightshielding electrode layer covers the first active layer, and the lightshielding electrode layer is electrically connected to the secondsource.
 16. The display panel according to claim 10, wherein theconductive particle comprises one of boron ions, nitrogen ions, orphosphorus ions.
 17. The display panel according to claim 15, whereinthe light shielding electrode layer comprises one of molybdenum, copper,chromium, tungsten, tantalum, or titanium.
 18. A method for preparing adisplay panel, the display panel comprises a substrate and a drivecircuit layer on one side of the substrate, wherein the methodcomprises: step S1: providing a substrate, and forming at least a firstactive layer, a first gate insulating layer, a first gate layer, and aphotoresist layer on the substrate; wherein the first active layercomprises a first source doped region, a first channel region, a firstdrain doped region, a first diffusion region between the first sourcedoped region and the first channel region, and a second diffusion regionbetween the first drain doped region and the first channel region; stepS2: patterning the photoresist layer to form a first photoresist patternthat does not block the first source doped region and the first draindoped region of the first active layer; step S3: etching the first gatelayer and the first gate insulating layer by using the first photoresistpattern as a barrier layer, so that both thicknesses of the first gateinsulating layer corresponding to the first source doped region and thefirst drain doped region are smaller than a thickness corresponding tothe first diffusion region, the second diffusion region, and the firstchannel region; and simultaneously doping a conductive particle from thefirst gate insulating layer to the first source doped region and thefirst drain doped region; step S4: patterning the first photoresistpattern to form a second photoresist pattern, etching the first gatelayer and the first gate insulating layer by using the first photoresistpattern as a barrier layer again, so that each thickness of the firstgate insulating layer corresponding to the first diffusion region andthe second diffusion region is less than a thicknesses corresponding tothe first channel region; and stripping the second photoresist pattern;and step S5: forming an interlayer insulating layer on the first gateinsulating layer, and forming a first source and a first drain on theinterlayer insulating layer, wherein the first source and the firstdrain are electrically connected to the first source doped region andthe first drain doped region through a source contact hole and a draincontact hole, respectively.
 19. The method according to claim 18,wherein the conductive particle in the step S3 comprises one of boronions, nitrogen ions, or phosphorus ions.
 20. The method according toclaim 19, wherein both of doping concentrations of the conductiveparticle in the first source doped region and the first drain dopedregion are greater than that doping concentrations of the conductiveparticle in the first diffusion region and the second diffusion region;and both of doping concentrations of the conductive particle in thefirst diffusion region and the second diffusion region are greater thandoping concentration of the conductive particle in the first channelregion.